Table of Contents
This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project. The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs. The author includes everything an engineer needs for in-depth understanding of the Verilog language: Syntax, synthesis semantics, simulation and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book. For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book. A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test. A concluding presentation of special topics includes System Verilog and Verilog-AMS.
https://www.eecourse.com/course/214 《Verilog RTL编程实践》是以美国硅谷技术研究院的培训教材《Digital VLSI Design with Verilog》《Verilog数字VLSI设计教程》（中文翻译版）为参考教材开发的一门工程实践类课程。课程不仅是对Verilog语言的语义语法的理论描述，更重要的是从逻辑仿真工具和逻辑综合工具使用的角度，总结和升华对Verilog RTL编程技术。也涵盖重要Verilog编程知识技巧，尤其是测试平台搭建，主流状态机描.